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FEATURES
Avalanche Rugged Technology Rugged Gate Oxide Technology Lower Input Capacitance Improved Gate Charge Extended Safe Operating Area 175C Operating Temperature Lower Leakage Current: 10A (Max.) @ VDS = 60V Lower RDS(ON): 0.020 (Typ.)
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IRFZ44
BVDSS = 60 V RDS(on) = 0.024 ID = 50 A
TO-220
1 2 3
1.Gate 2. Drain 3. Source
Absolute Maximum Ratings
Symbol VDSS ID IDM VGS EAS IAR EAR dv/dt PD TJ , TSTG TL Characteristic Drain-to-Source Voltage Continuous Drain Current (TC=25C) Continuous Drain Current (TC=100C) Drain Current-Pulsed Gate-to-Source Voltage Single Pulsed Avalanche Energy Avalanche Current Repetitive Avalanche Energy Peak Diode Recovery dv/dt Total Power Dissipation (TC=25C) Linear Derating Factor Operating Junction and Storage Temperature Range Maximum Lead Temp. for Soldering Purposes, 1/8 from case for 5-seconds
(2) (1) (1) (3) (1)
Value 60 50 35.4 200 20 857 50 12.6 5.5 126 0.84 - 55 to +175
Units V A A V mJ A mJ V/ns W W/C
C 300
Thermal Resistance
Symbol RJC RCS RJA Characteristic Junction-to-Case Case-to-Sink Junction-to-Ambient Typ. -0.5 -Max. 1.19 -62.5 C/W Units
Rev. B
(c)1999 Fairchild Semiconductor Corporation
IRFZ44
Electrical Characteristics (TC=25C unless otherwise specified)
Symbol BVDSS BV/TJ VGS(th) IGSS IDSS RDS(on)
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Characteristic Drain-Source Breakdown Voltage Breakdown Voltage Temp. Coeff. Gate Threshold Voltage Gate-Source Leakage , Forward Gate-Source Leakage , Reverse Drain-to-Source Leakage Current Static Drain-Source On-State Resistance Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Total Gate Charge Gate-Source Charge Gate-Drain ( Miller ) Charge
Min. Typ. Max. Units 60 -2.0 -----------------0.063 ------32.6 590 220 20 16 68 70 64 12.3 23.6 --4.0 100 -100 10 100 0.024 -680 255 40 40 140 140 83 --nC ns A V V nA
Test Condition VGS=0V,ID=250A
V/C ID=250A VGS=20V VGS=-20V VDS=60V
See Fig 7
VDS=5V,ID=250A
VDS=48V,TC=150C VGS=10V,ID=25A VDS=30V,ID=25A
(4) (4)
gfs Ciss Coss Crss td(on) tr td(off) tf Qg Qgs Qgd
1770 2300 pF
VGS=0V,VDS=25V,f =1MHz
See Fig 5
VDD=30V,ID=50A, RG=9.1
See Fig 13
VDS=48V,VGS=10V, ID=50A
(4) (5)
See Fig 6 & Fig 12 (4) (5)
Source-Drain Diode Ratings and Characteristics
Symbol IS ISM VSD trr Qrr Characteristic Continuous Source Current Pulsed-Source Current Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge
(1) (4)
Min. Typ. Max. Units --------85 0.24 50 200 1.8 --A V ns C
Test Condition Integral reverse pn-diode in the MOSFET TJ=25C,IS=50A,VGS=0V TJ=25C,IF=50A diF/dt=100A/s
(4)
Notes; (1) Repetitive Rating: Pulse Width Limited by Maximum Junction Temperature (2) L=0.4mH, IAS=50A, VDD=25V, RG=27, Starting TJ =25C (3) ISD 50A, di/dt 350A/s, VDD BV DSS , Starting TJ =25C (4) Pulse Test : Pulse Width = 250s, Duty Cycle 2% (5) Essentially Independent of Operating Temperature
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IRFZ44
Fig 2. Transfer Characteristics
12 0
Fig 1. Output Characteristics
VGS
12 0
Top :
ID , Drain Current [A]
ID , Drain Current [A]
15 V 10 V 8.0 V 7.0 V 6.0 V 5.5 V 5.0 V Bottom : 4.5 V
11 0 1 5 oC 7 10 0
11 0
2 oC 5
@ Nt s: oe 1 2 0 s P l e T s .5 us et 2 T = 2 oC .C 5 1 0 -1 0 1 0 1 0
0
- 5 oC 5 1 0
1
@N ts : oe 1 V =0 V . GS 2 V =3 V . DS 0 3 2 0 s P l e T s .5 us et 6 8 1 0
1 -1 0
2
4
VDS , Drain-Source Voltage [V]
VGS , Gate-Source Voltage [V]
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Fig 3. On-Resistance vs. Drain Current
00 .4
Fig 4. Source-Drain Diode Forward Voltage IDR , R rs D in Cu ent [A] eve e ra rr
12 0
RDS(on) , [ ] Dr Sour O sis e ain- ce n-Re tanc
00 .3
V =1 V 0 GS
00 .2
11 0
00 .1
V =2 V 0 GS @ N t : T = 2 oC oe J 5
1 5 oC 7 2 oC 5
0
@N ts : oe 1 V =0 V . GS 2 2 0 s P l e T s .5 us et
00 .0 0
4 0
8 0
10 2
10 6
20 0
20 4
1 0 04 06 08 10 12 14 16 18 20 22 24 26 28 30 ..............
I , Dra C nt [A] in urre D Fig 5. Capacitance vs. Drain-Source Voltage
30 50 C = C + C (C = so td ) iss gs gd ds h r e C =C +C oss ds gd C =C rss gd
VSD , S ce ai Vol ge [ our -Dr n ta V] Fig 6. Gate Charge vs. Gate-Source Voltage
20 80
1 0
V =1 V 2 DS V =3 V 0 DS V =4 V 8 DS
20 10
C oss
VGS , Gate-Source Voltage [V]
C iss
Capacitance [pF]
10 40 C rss 70 0
@ Nt s: oe 1 V =0 V . GS 2 f =1 M z . H
5
@N ts :I =5 . A oe 00 D 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0
00 1 0
1 0
1
VDS , Drain-Source Voltage [V]
QG , Total Gate Charge [nC]
IRFZ44
Fig 7. Breakdown Voltage vs. Temperature
12 . 25 .
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Fig 8. On-Resistance vs. Temperature
BVDSS , (Normalized) Drain-Source Breakdown Voltage
11 .
RDS(on) , (Normalized) Drain-Source On-Resistance
20 .
10 .
15 .
09 .
@ Nt s: oe 1 V =0 V . GS 2 I = 2 0 A .D 5 -0 5 -5 2 0 2 5 5 0 7 5 10 0 15 2
o
10 .
@N ts : oe 1 V =1 V . GS 0 2 I =5 A .D2 -0 5 -5 2 0 2 5 5 0 7 5 10 0 15 2 10 5 15 7 20 0
08 . -5 7
10 5
15 7
20 0
05 . -5 7
TJ , Junction Temperature [ C]
TJ , Junction Temperature [oC]
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Fig 9. Max. Safe Operating Area
13 0 O ea in i T i Ae pr to n hs ra i L m t d b R DS(on) s i ie y 1 s 0 1 0 s 0 1m s 1m 0s 11 0 D C
Fig 10. Max. Drain Current vs. Case Temperature
6 0
ID , Drain Current [A]
1 0
2
ID , Drain Current [A]
5 0
4 0
3 0
2 0
10 0
@ Nt s: oe 1 T = 2 oC .C 5 2 T = 1 5 oC .J 7 3 Sn l P le . ig e u s
1 0
1 -1 0 0 1 0
11 0
12 0
0 2 5
5 0
7 5
10 0
15 2
10 5
15 7
VDS , Drain-Source Voltage [V]
Tc , Case Temperature [oC]
Fig 11. Thermal Response
Thermal Response
100 D=0.5 @ Notes : 1. Z J C (t)=1.19 o C/W Max. 2. Duty Factor, D=t1 /t2 3. TJ M -TC =PD M *Z J C (t)
PDM
0.2 10- 1 0.1 0.05
Z JC(t) ,
0.02 0.01
single pulse
t1 t2
10- 2 - 5 10
10- 4
10- 3
10- 2
10- 1
100
101
t1 , Square Wave Pulse Duration
[sec]
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IRFZ44
Fig 12. Gate Charge Test Circuit & Waveform
Current Regulator
50k 12V 200nF 300nF
Same Type as DUT
VGS Qg
10V
VDS VGS DUT
3mA
Qgs
Qgd
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R1
Current Sampling (IG) Resistor
R2
Current Sampling (ID) Resistor
Charge
Fig 13. Resistive Switching Test Circuit & Waveforms
RL Vout Vin RG DUT Vin 10V
td(on) t on tr td(off) t off tf 10%
Vout VDD
( 0.5 rated VDS )
90%
Fig 14. Unclamped Inductive Switching Test Circuit & Waveforms
LL VDS
Vary tp to obtain required peak ID
BVDSS 1 EAS = ---- LL IAS2 -------------------2 BVDSS -- VDD BVDSS IAS C VDD VDD
tp
ID
RG DUT 10V
tp
ID (t) VDS (t) Time
IRFZ44
Fig 15. Peak Diode Recovery dv/dt Test Circuit & Waveforms
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DUT
+ VDS --
IS L Driver RG VGS
Same Type as DUT
VGS
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VDD
dv/dt controlled by RG IS controlled by Duty Factor D
VGS ( Driver )
Gate Pulse Width D = -------------------------Gate Pulse Period
10V
IFM , Body Diode Forward Current
IS ( DUT ) IRM
di/dt
Body Diode Reverse Current
VDS ( DUT )
Body Diode Recovery dv/dt
Vf
VDD
Body Diode Forward Voltage Drop
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.
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ACExTM CoolFETTM CROSSVOLTTM E2CMOSTM FACTTM FACT Quiet SeriesTM FAST(R) FASTrTM GTOTM HiSeCTM
DISCLAIMER
ISOPLANARTM MICROWIRETM POPTM PowerTrenchTM QSTM Quiet SeriesTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 TinyLogicTM
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life support device or system whose failure to perform can systems which, (a) are intended for surgical implant into be reasonably expected to cause the failure of the life the body, or (b) support or sustain life, or (c) whose support device or system, or to affect its safety or failure to perform when properly used in accordance with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.
Preliminary
First Production
No Identification Needed
Full Production
Obsolete
Not In Production
This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.

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